A well known ROM in general is shown in FIG. 2. Referring to FIG. 2, a circuit structure of the ROM will be described hereinbelow. In order to simplify the description, some of N-channel MOS transistors (hereinafter, NMOS) are represented by a simplified sketch as shown in FIG. 3, and some of P-channel MOS transistors (hereinafter, PMOS) are also represented by a simplified sketch as shown in FIG. 4.
The ROM shown in FIG. 2 is constituted of a memory cell block MC for storing data, a Y-decoder YD for selecting (activating) word-lines Y1 to Y8, and an X-decoder XD for selecting bit-lines X1 to X16 (reference numerals of word-lines Y4 to Y7 and bit-lines X4 to X15 are not shown in FIG. 2). The Y-decoder YD is connected to a word-line discharge circuit WD in which a voltage of V.sub.SS level as a ground potential is supplied to the word-lines Y1 to Y8. And the word-lines Y1 to Y8 are connected to a word-line precharge circuit WP in which a voltage of V.sub.DD level as a power supply potential is supplied thereto (reference numerals of decode-lines AY4 to AY7 are not shown in FIG. 2).
On the other hand, decode-lines AX1 to AX16 in the X-decoder XD are commonly connected to a data terminal 225 (reference numerals of decode-lines AX4 to AX15 are not shown in FIG. 2). Then, the data terminal 225 is connected to a bit-line precharge circuit BP, in which the voltage of V.sub.DD level is supplied to the bit-lines X1 to X16, and further, to a data output terminal 221 through a data output buffer OB. Further, the bit-lines X1 to X16 are connected to a data output enable circuit DOE in which the voltage of V.sub.SS level is supplied thereto.
Next, each circuit structure in the ROM will be described in detail.
The memory cell block MC has a capacity of 128 bits and memory locations defined at cross-over positions at which respective word-lines and bit-lines intersect with each other. Then, NMOSs for storing data are arranged on the respective memory locations. For example, NMOSs h1 and h2 are connected in series to the bit-line X1 so that a gate of the NMOS h1 is connected to the word-line Y3 and a gate of the NMOS h2 is connected to the word-line Y7. That is, the NMOS h1 is arranged on the memory location (X1, Y3) defined by the word-line Y3 and the bit-line X1, likewise, the NMOS h2 is arranged on the memory location (X1, Y7) defined by the word-line Y7 and the bit-line X1. Further, any other NMOSs for storing data are not substantially arranged on the other memory locations of the bit-line X1.
Although all of the memory locations of the bit-line X1 practically have NMOSs respectively, no NMOS apparently appear except the NMOSs h1 and h2 by forming short-circuit between the sources and the drains with aluminum wire or the like, otherwise, by forming quasi short-circuit by using a method of ion implantation.
The Y-decoder YD is constituted of Y address terminals 209, 211, 213 to which Y address signals are provided, inverters e1 to e6 for inverting the Y address signals, and Y decode-lines AY1 to AY8 respectively connected to the word-lines Y1 to Y8. Each of the decode-lines is constituted of three NMOSs connected in series to one another, therefore, the Y-decoder YD is constituted of 24 NMOSs in total. These NMOSs are turned on in response to the Y address signals provided to Y address terminals 209, 211, 213.
On this moment, there exists only one Y decode-line on which all the three NMOSs connected in series are turned on. It is selected, a word-line connected to the selected Y decode-line.
The word-line discharge circuit WD is constituted of a precharge signal input terminal 229 to which a precharge signal P1 is provided, an inverter e7, NMOSs g41 to g48, and a V.sub.SS terminal 231 to which the voltage of V.sub.SS level is supplied (reference numerals of NMOSs g44 to g47 are not shown in FIG. 2). Each source of the NMOSs g41 to g48 is commonly connected to the V.sub.SS terminal 231, each drain is connected to respective decode-lines AY1 to AY8, and each gate is commonly connected to an output terminal of the inverter e7. Then, the word-line discharge circuit WD supplies V.sub.SS level (discharging) to respective decode-lines AY1 to AY8 in response to the precharge signal P1 changing to a L level. As a result, the level of the Y decode-line selected by the Y address signal is turned to V.sub.SS level, and the level of the Y word-line connected to the Y decode-line is turned to V.sub.SS level. That is, the word-line discharge circuit WD discharges the level of the word-line selected by the Y address signal in response to the precharge signal P1 changing to the L level.
On the other hand, the word-line precharge circuit WP is constituted of a precharge signal input terminal 227 to which the precharge signal P1 is provided, an inverter e8, PMOSs g51 to g58, and a V.sub.DD terminal 233 to which the voltage of V.sub.DD level is supplied (reference numerals of PMOSs g54 to g57 are not shown in FIG. 2). Each source of the PMOSs g51 to g58 is commonly connected to the V.sub.DD terminal 233, each drain is connected to respective word-lines Y1 to Y8, and each gate is connected to an output terminal of inverter e8. The word-line precharge circuit WP supplies the voltage of V.sub.DD level (precharging) to respective word-lines Y1 to Y8 in response to the precharge signal P1 changing to a H level.
The X-decoder XD is constituted of X address terminals 201, 203, 205, 207 to which X address signals are provided, inverters d1 to d8 for inverting the X address signals, X decode-lines AX1 to AX16 connected to the bit-lines X1 to X16 respectively. Each of the X decode-lines is constituted of four NMOSs connected in series to one another, therefore, the X-decoder XD is constituted of 64 NMOSs in total. Then, the NMOSs are turned on in response to the X address signals provided to X address terminals 201, 203, 205, 207. On this moment, there exists only one X decode-line on which the four NMOSs connected in series are turned on. It is selected, a bit-line connected to the selected X decode-line. The operation of the X-decoder is the same as that of the Y-decoder.
The bit-line precharge circuit BP is constituted of a precharge signal input terminal 219 to which a precharge signal P2 is provided, an inverter d9, PMOS d10, and a V.sub.DD terminal 223 to which the voltage of V.sub.DD level is supplied.
Then, the bit-line precharge circuit BP supplies V.sub.DD level to the data terminal 225 in response to the precharge signal P2 changing to the H level. As a result, an X decode-line selected by the X address signal is turned to V.sub.DD level, and only one of the bit-lines connected to the selected X decode-line is turned to V.sub.DD level (precharge).
Meanwhile, the data output enable circuit DOE is constituted of a precharge signal input terminal 215 to which the precharge signal P2 is provided, an inverter d13, and a V.sub.SS terminal 217 to which the voltage of V.sub.SS level is supplied. Each drain of the NMOSs f501 to f516 is connected to respective bit-lines X1 to X16, each source is commonly connected to the V.sub.SS terminal 217, and each gate is connected to an output terminal of the inverter d13. Then, the data output enable circuit DOE supplies V.sub.SS level to the respective bit-lines in response to the precharge signal P2 changing to the L level. As a result, a data on a memory location selected by the X address signal and the Y address signal appears at the data terminal 225 through the corresponding decode-line.
The data output buffer OB is constituted of two inverters d11 and d12, and a data output terminal 221. The data output buffer OB outputs the data (electric potential), which appears at the data terminal 225, from the data output terminal 221.
FIG. 5 is a timing charts illustrating waveforms of data read out from the above-mentioned ROM. In the method of reading data, the precharge signals P1 and P2 rise to the H level at the same time, thereby a word-line and a bit-line being precharged. Then, X and Y address signals are fixed, and the prescribed memory location is selected. Finally, the precharge signals P1 and P2 are fallen to the L level so that the data on the selected memory location are read out.
However, the method for reading data mentioned above has accompanied a problem that, when the read cycle operates at a higher speed, data on memory locations may not be accurately read out.
For example, in FIG. 2, when a data "1" on the memory location arranging the NMOS h1 (memory location arranging NMOS holds "1") is continuously read many times, the same bit-line is repeatedly precharged, therefore, even the source and the drain of the NMOS h2 arranged at a position far from the data terminal 225 are charged to V.sub.DD -V.sub.TN level. And thereafter, when a data "0" on a memory location i1 shown in FIG. 2, for example, is read (memory location not arranging NMOS holds "0"), an electric charge which is charged to sources and drains of the NMOSs h1 and h2 in the last operation of reading data "1" can not be completely discharged in a short time, and further, a level of the data terminal 225 can not be completely turned to V.sub.SS level ("0") in some cases. That is, as the read cycle operates at a higher speed, the data "1" may be outputted from the data output terminal 221 in spite of the fact that the data "0" is read.
The phenomenon is remarkable revealed more and more when the read cycle is accelerated and the number of NMOSs for storing data increases.
The problem can be solved by reducing the number of columns of NMOSs for storing data and dividing the memory cell block into plural blocks. Such an attempt for solving the problem, however, is not preferable on the ground that dividing the memory cell block into plural blocks causes enlarged chip size of LSI so as to be required to provide plural X-decoders and Y-decoders.
Further, although it can be considered to extend a time period of turning on the NMOSs f501 to f516 which discharge electric potential of bit-lines, it is not also preferable because it can reduce the read speed of ROM.